The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2020
Filed:
Jan. 02, 2019
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); G11C 7/20 (2006.01); G11C 29/12 (2006.01); G11C 29/32 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/023 (2013.01); G11C 7/1012 (2013.01); G11C 7/20 (2013.01); G11C 7/22 (2013.01); G11C 29/12015 (2013.01); G11C 29/32 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/3202 (2013.01);
Abstract
Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.