The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Dec. 31, 2016
Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

G. Glenn Henry, Austin, TX (US);

Kim C. Houck, Austin, TX (US);

Parviz Palangpour, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/00 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06N 3/04 (2013.01); G06N 3/082 (2013.01);
Abstract

A memory holds D rows of N words and receives an address having logD bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit that performs an operation thereon to accumulate a result, and multiplexing logic receiving memory word J, and for PUs 0 to (N/2)−1 also memory word J+(N/2). In a first mode, the multiplexing logic of PUs 0 to N−1 selects word J to output to the first register. In a second mode: when the extra bit is a zero, the multiplexing logic of PUs 0 to (N/2)−1 selects word J to output to the first register, and when the extra bit is a one, the multiplexing logic of PUs 0 through (N/2)−1 selects word J+(N/2) to output to the first register.


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