The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Dec. 23, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Soila P. Kavulya, Beaverton, OR (US);

Michael R. Alton, Portland, OR (US);

Abolfazl Shahbazi, West Linn, OR (US);

Todd Lisonbee, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 16/2453 (2019.01); G06F 16/2455 (2019.01);
U.S. Cl.
CPC ...
G06F 16/24545 (2019.01); G06F 16/24544 (2019.01); G06F 16/24554 (2019.01);
Abstract

An apparatus for optimizing a skewed join is described herein. The apparatus includes logic, at least partially including hardware logic, to determine that a dataset for the skewed join comprises a skewed key that does not fit in memory. The apparatus also includes logic to model the skewed join as a queue. The apparatus also includes logic to estimate a cost of the skewed join based on the modeled queue. The apparatus evaluates different join techniques, and partitioning strategies for the skewed join, and chooses the plan with the lowest cost.


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