The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2020

Filed:

Jun. 18, 2018
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Doe Hyun Yoon, San Jose, CA (US);

Naveen Muralimanohar, Santa Clara, CA (US);

Jichuan Chang, Sunnyvale, CA (US);

Parthasarathy Ranganathan, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/0655 (2013.01); G06F 3/0665 (2013.01); G06F 3/0688 (2013.01); G06F 11/108 (2013.01); G06F 3/0656 (2013.01); G06F 3/0689 (2013.01); G06F 2211/1054 (2013.01); G06F 2211/1066 (2013.01);
Abstract

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.


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