The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Dec. 27, 2018
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventor:

Yasuhiro Kagawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/266 (2013.01); H01L 21/26506 (2013.01); H01L 29/1608 (2013.01); H01L 29/4236 (2013.01); H01L 29/66068 (2013.01); H02M 7/53875 (2013.01);
Abstract

A first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type provided in an upper layer part thereof, a second semiconductor region of the first conductivity type provided in the upper layer part thereof, a gate trench penetrating through the first and second semiconductor regions in a thickness direction and a bottom surface thereof reaching inside of the first semiconductor layer, a gate insulating film in the gate trench, a gate electrode embedded in the gate trench, a second semiconductor layer of the second conductivity type provided so as to extend, from the bottom surface of the gate trench, a third semiconductor layer of the second conductivity type extending to a position deeper than the bottom surface of the gate trench, and a fourth semiconductor layer of the first conductivity type interposed between the second semiconductor layer and the third semiconductor layer in the position deeper than the bottom surface of the gate trench.


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