The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Feb. 15, 2017
Applicant:

South China University of Technology, Guangdong, CN;

Inventors:

Hong Wang, Guangdong, CN;

Quanbin Zhou, Guangdong, CN;

Qixin Li, Guangdong, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66431 (2013.01); H01L 21/02507 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 29/7786 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02505 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01);
Abstract

An enhancement-mode GaN-based HEMT device on Si substrate and a manufacturing method thereof. The device includes a Si substrate, an AlN nucleation layer, AlGaN transition layers, an AlGaN buffer layer, a low temperature AlN insertion layer, an AlGaN main buffer layer, an AlGaN/GaN superlattice layer, an GaN channel layer, and an AlGaN barrier layer. Both sides of a top end of the HEMT device are a source electrode and a drain electrode respectively, and a middle of the top end is a gate electrode. A middle of the AlGaN barrier layer is etched through to form a recess, and a bottom of the recess is connected to the GaN channel layer. A passivation protective layer and a gate dielectric layer are deposited on the bottom of the recess, and the gate electrode is located above the dielectric layer.


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