The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Feb. 23, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Kwan-Yong Lim, Niskayuna, NY (US);

Ryan Ryoung-Han Kim, Albany, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); G11C 8/14 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 27/105 (2006.01); H01L 21/48 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 8/14 (2013.01); H01L 21/486 (2013.01); H01L 21/76838 (2013.01); H01L 23/50 (2013.01); H01L 23/5226 (2013.01); H01L 27/1052 (2013.01);
Abstract

A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PUand PU) transistors, and first and second pull-down (PDand PD) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PUand PU. A second bottom electrode connects bottom SD regions of PDand PD. A first shared contact connects the top SD region of PUto the gate structure of PU. A second shared contact connects the top SD region of PDto the gate structure of PD. A first top electrode is connected to the top SD regions of PG, PUand the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG, PUand the first shared contact to define a second storage node of the memory cell.


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