The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Apr. 11, 2018
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Jian Wu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7685 (2013.01); H01L 21/76816 (2013.01); H01L 21/76843 (2013.01); H01L 21/76897 (2013.01); H01L 21/823821 (2013.01); H01L 23/5226 (2013.01); H01L 27/0924 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an active region on the substrate, an electrode in the active region, and an interlayer dielectric layer covering the active region and the electrode. The method also includes etching the interlayer dielectric layer to form a contact hole exposing the electrode, forming a conductive adhesion layer on a bottom and sidewalls of the contact hole, and forming a contact member on the conductive adhesion layer filling the contact hole. The conductive adhesion layer at the bottom and sidewalls of the contact hole prevents the electrode from being oxidized while forming the contact member, thereby effectively reducing the contact resistance and the barrier height of the semiconductor device.


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