The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jan. 11, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ryan P. King, Lagrangeville, NY (US);

Stephen Glancy, Yorktown, VA (US);

John S. Bialas, Jr., South Burlington, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 29/10 (2006.01); G11C 11/4093 (2006.01); G11C 29/50 (2006.01); G11C 7/10 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 7/1066 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/10 (2013.01); G11C 29/50012 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.


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