The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Apr. 04, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Eberhard Engler, Tuebingen, DE;

Christian Jacobi, West Park, NY (US);

Timothy J. Slegel, Staatsburg, NY (US);

Scott B. Swaney, Germantown, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 11/36 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/362 (2013.01); G06F 11/0715 (2013.01); G06F 11/0757 (2013.01); G06F 11/0778 (2013.01); G06F 2201/81 (2013.01);
Abstract

An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.


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