The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2020
Filed:
Mar. 01, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/07 (2006.01); G11C 29/02 (2006.01); G06F 12/0813 (2016.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/02 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/406 (2006.01); G11C 5/14 (2006.01); H04L 9/08 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0793 (2013.01); G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0638 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 11/079 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 12/023 (2013.01); G06F 12/0802 (2013.01); G06F 12/0813 (2013.01); G06F 13/1663 (2013.01); G06F 13/1678 (2013.01); G06F 13/1689 (2013.01); G06F 13/1694 (2013.01); G06F 13/4234 (2013.01); G06F 13/4243 (2013.01); G06F 13/4282 (2013.01); G11C 5/148 (2013.01); G11C 7/1003 (2013.01); G11C 7/1072 (2013.01); G11C 7/222 (2013.01); G11C 11/40618 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); H04L 9/0869 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/60 (2013.01); G11C 5/04 (2013.01); G11C 7/1063 (2013.01);
Abstract
Provided are a method and apparatus for using an error signal to indicate a write request error and write request acceptance performing error handling operations using error signals. A memory module controller detects a write error for a write request in a memory module and asserts an error signal on a bus to a host memory controller in response to detecting the write error.