The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Jun. 19, 2019
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventor:

Chien-Chen Lin, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 1/02 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0271 (2013.01); H01L 23/49816 (2013.01); H01L 24/04 (2013.01); H01L 24/12 (2013.01); H01L 24/19 (2013.01); H01L 24/32 (2013.01); H05K 3/4614 (2013.01); H05K 3/4644 (2013.01); H05K 3/4697 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01); H01L 2924/3511 (2013.01); H05K 2203/061 (2013.01);
Abstract

A circuit carrier structure includes a glass substrate, an anti-warping layer, a conductive layer, a build-up circuit layer, and a conductive via. The glass substrate has a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate. The anti-warping layer is disposed on the first surface of the glass substrate and has at least one first opening and a second opening. The conductive layer is disposed in the first opening of the anti-warping layer. The build-up circuit layer is disposed on the second surface of the glass substrate. The conductive via penetrates the glass substrate. The conductive via is disposed corresponding to the first opening of the anti-warping layer, and the through groove is disposed corresponding to the second opening of the anti-warping layer, and the through groove exposes a portion of the build-up circuit layer.


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