The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Jul. 25, 2018
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Vijay Ganwani, Pune, IN;

Ankit Sethi, Pune, IN;

Sudhir Srinivasa, Campbell, CA (US);

Sih-Yu Lin, Newark, CA (US);

Yui Lin, Palo Alto, CA (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01); G06F 11/10 (2006.01); H03M 13/09 (2006.01); H04W 28/04 (2009.01); H04W 76/23 (2018.01);
U.S. Cl.
CPC ...
H04L 1/0061 (2013.01); G06F 11/1004 (2013.01); H03M 13/09 (2013.01); H04L 1/0041 (2013.01); H04W 28/04 (2013.01); H04L 1/0026 (2013.01); H04W 76/23 (2018.02);
Abstract

The present disclosure describes methods and apparatuses for phase-based cyclic redundancy check (CRC) verification for wireless communication. In some aspects, a soft phase value and a sliced phase value are received for a symbol of a data packet, the data packet received via a wireless interface. An error measurement is determined for the symbol based on the soft phase value and the sliced phase value. The error measurement for the symbol is then compared to an error measurement threshold for detecting symbol-level errors in the data packet. Based on the error measurement exceeding an error measurement threshold, a bit error can be detected in the data packet, which may have passed CRC. By detecting the bit error despite a CRC pass, the bit error can be indicated to higher-level entity of the wireless interface. This can be effective to prevent the bit error from impairing operation of the higher-level entity.


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