The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10573526 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 25, 2020

Filed:

Sep. 15, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sunit S. Mahajan, Clifton Park, NY (US);

Bachir Dirahoui, Bedford Hills, NY (US);

Richard Wise, Los Gatos, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/00 (2006.01); H01L 21/3065 (2006.01); H01J 37/32 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01); H01J 37/32009 (2013.01); H01J 37/32532 (2013.01); H01L 21/6833 (2013.01); H01L 21/76898 (2013.01); H01L 29/66363 (2013.01); H01J 2237/334 (2013.01);
Abstract

A plasma processing apparatus for reactive ion etching a wafer includes a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer. Both p− and n+ layers have exposed peripheral edges. Also provided is an anode comprising the plasma, a cathode comprising the wafer chuck, and a gate comprising the peripheral edge of the n+ layer. A coating layer is formed on a portion of the peripheral edge of the n+ layer. The coating layer reduces charge flow to a portion of the semiconductor wafer below the coating layer.


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