The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Aug. 16, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Carl Z. Zhou, Plano, TX (US);

Keith A. Remack, Richardson, TX (US);

John A. Rodriguez, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/22 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 11/221 (2013.01); G11C 29/028 (2013.01); G11C 29/50016 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 29/50 (2013.01);
Abstract

Disclosed embodiments include a testing system that electrically connects to an integrated circuit (IC) having ferroelectric memory (FRAM) cells. The testing system programs the FRAM cells to a first data state and then iteratively reads the programmed cells at a plurality of reference voltages to identify a reference voltage limit that indicates a first occurrence at which at least one of the cells fails to return the first data state when read. Iteratively reading the cells includes reading each cell at an initial reference voltage at which all the cells return the first data state, and then reading each of the programmed cells at each of the remaining reference voltages by incrementally changing the initial reference voltage in one direction until the reference voltage limit is identified. The testing system sets the reference in the IC at an operating level based on the reference voltage limit.


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