The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2020
Filed:
Feb. 27, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Robert J. Royer, Jr., Portland, OR (US);
Blaise Fanning, Folsom, CA (US);
Eng Hun Ooi, Georgetown, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0866 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 11/1064 (2013.01); G06F 11/1048 (2013.01); G06F 12/0866 (2013.01); G06F 12/084 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/313 (2013.01);
Abstract
Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.