The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2020
Filed:
Jan. 29, 2018
Applicant:
Raytheon Company, Waltham, MA (US);
Inventor:
Jeffrey R. LaRoche, Andover, MA (US);
Assignee:
Raytheon Company, Waltham, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 23/485 (2006.01); H01L 29/417 (2006.01); H01L 29/778 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 21/8252 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 29/45 (2006.01); H01L 29/47 (2006.01); H01L 29/49 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/28264 (2013.01); H01L 21/28575 (2013.01); H01L 21/28581 (2013.01); H01L 21/76805 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 21/8252 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 29/4175 (2013.01); H01L 29/452 (2013.01); H01L 29/475 (2013.01); H01L 29/495 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 21/28587 (2013.01); H01L 21/76816 (2013.01); H01L 29/2003 (2013.01); H01L 29/41758 (2013.01); H01L 29/7787 (2013.01);
Abstract
A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.