Method of forming vertical channel devices

Abstract

The disclosed technology generally relates semiconductor devices and more particularly to vertical channel devices and methods of forming the vertical channel devices. According to one aspect, a method of forming a vertical channel device includes forming on a semiconductor substrate a plurality of vertical channel structures. The method additionally includes forming gates, where each of the gates wraps around one of the vertical channel structures. The method additionally includes embedding the gates in a first dielectric layer and exposing top portions of the vertical channel structures. The method additionally includes forming top electrodes on corresponding top portions of the vertical channel structures. The method additionally includes forming sidewall etch barriers on sidewalls of each of the top electrodes. The method additionally includes forming a second dielectric layer covering the first dielectric layer and the top electrodes. The method additionally includes etching a set of vertically extending gate contact holes through the first and second dielectric layers and selectively against the sidewall etch barriers, where each of the gate contact holes exposes one of the gates adjacent to one of the top electrodes. The method further includes filling the set of gate contact holes with a conductive material. A vertical channel device fabricated using the method is also disclosed according another aspect.