The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Mar. 14, 2016
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventors:

Norihiro Kobayashi, Takasaki, JP;

Osamu Ishikawa, Takasaki, JP;

Kenji Meguro, Nagano, JP;

Taishi Wakabayashi, Nagano, JP;

Hiroyuki Oonishi, Ueda, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 21/20 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/322 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2007 (2013.01); H01L 21/02 (2013.01); H01L 21/3226 (2013.01); H01L 21/76254 (2013.01); H01L 27/12 (2013.01);
Abstract

A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 Ω·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.


Find Patent Forward Citations

Loading…