The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Feb. 14, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kenji Sakurada, Yamato, JP;

Masanobu Shirakawa, Chigasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 11/419 (2006.01); G11C 16/34 (2006.01); G11C 7/06 (2006.01); G11C 16/32 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/06 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/34 (2013.01); G11C 16/0483 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a first memory cell; a first latch circuit; and a second latch circuit. The first latch circuit and the second latch circuit are associated with the first memory cell. When the semiconductor memory device receives, from an external device, a first address designating one of the first latch circuit and the second latch circuit and a read command for data of the first memory cell, data is read from the first memory cell and the read data is held in the one of the first latch circuit and the second latch circuit corresponding to the first address.


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