The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Sep. 25, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Siddhartha Chhabra, Portland, OR (US);

Reouven Elbaz, Hillsboro, OR (US);

Krishnakumar Narasimhan, Beaverton, OR (US);

Prashant Dewan, Portland, OR (US);

David M. Durham, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); H04L 9/32 (2006.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01); G06F 21/85 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01); G06F 21/85 (2013.01); H04L 9/3242 (2013.01);
Abstract

Technologies for secure memory usage include a computing device having a processor that includes a memory encryption engine and a memory device coupled to the processor. The processor supports multiple processor usages, such as secure enclaves, system management firmware, and a virtual machine monitor. The memory encryption engine is configured to protect a memory region stored in the memory device for a processor usage. The memory encryption engine restricts access to one or more configuration registers to a trusted code base of the processor usage. The processor executes the processor usage and the memory encryption engine protects contents of the memory region during execution. The memory encryption engine may access integrity metadata based on the address of the protected memory region. The memory encryption engine may prepare top-level counter metadata for entering a low-power state. Other embodiments are described and claimed.


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