The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Jun. 04, 2019
Applicants:

Avary Holding (Shenzhen) Co., Limited., Shenzhen, CN;

Hongqisheng Precision Electronics (Qinhuangdao) Co., Ltd., Qinhuangdao, CN;

Inventors:

Rih-Sin Jian, New Taipei, TW;

Xiao-Wei Kang, Shenzhen, CN;

Li Yang, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/42 (2006.01); H05K 3/46 (2006.01); G11B 5/48 (2006.01); H05K 1/05 (2006.01); H05K 1/02 (2006.01); H05K 1/14 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4685 (2013.01); G11B 5/484 (2013.01); G11B 5/486 (2013.01); H05K 1/0265 (2013.01); H05K 1/0298 (2013.01); H05K 1/056 (2013.01); H05K 1/112 (2013.01); H05K 1/115 (2013.01); H05K 1/144 (2013.01); H05K 3/427 (2013.01); H05K 1/0245 (2013.01); H05K 3/4611 (2013.01); H05K 2201/0183 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/09727 (2013.01); H05K 2201/09881 (2013.01); H05K 2203/0323 (2013.01);
Abstract

A method for manufacturing a high-current printed circuit board, comprising: providing a circuit substrate comprising a substrate layer; a first circuit layer formed on the substrate layer; and a second circuit layer formed on the substrate layer and facing away from the first circuit layer, wherein first conductive circuits are defined on the first circuit layer, second conductive circuits are defined on the second circuit layer, and a line width of each of the first conductive circuits is greater than a line width of each of the second conductive circuits; and forming buffering circuits by plating, wherein the buffering circuits are electrically connected the first circuit layer to the second circuit layer; wherein a line width of each of the buffering circuits is greater than the line width of each of the second conductive circuits.


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