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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10559594 B1

PDFFull Text
Date of Patent:
Feb. 11, 2020

Filed:

Apr. 11, 2017

Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors

Applicants:

Ahmad Tarakji, Sacramento, CA (US);

Nirmal Chaudhary, Leesburg, VA (US);

Inventors:

Ahmad Tarakji, Sacramento, CA (US);

Nirmal Chaudhary, Leesburg, VA (US);

Assignee:

Other;

Attorney:
Primary Examiner:

Stephen M Bradley

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 23/00 (2006.01); H01L 29/786 (2006.01); H01L 27/02 (2006.01); H01L 21/8226 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/76802 (2013.01); H01L 21/8226 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 27/0207 (2013.01); H01L 29/78648 (2013.01); H01L 2224/83895 (2013.01); H01L 2224/83896 (2013.01);
Abstract

A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

Find Patent Forward Citations

Tarakji, Ahmad. (2020). Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors (U.S. Patent No. 10559594). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10559594

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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