The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Jun. 14, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Perry H. Pelley, Austin, TX (US);

Anirban Roy, Austin, TX (US);

Gayathri Bhagavatheeswaran, Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01); G11C 11/22 (2006.01); G11C 16/10 (2006.01); G11C 11/16 (2006.01); G11C 8/14 (2006.01); G11C 11/406 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 7/10 (2013.01); G11C 7/1096 (2013.01); G11C 8/14 (2013.01); G11C 11/1675 (2013.01); G11C 11/2275 (2013.01); G11C 11/40603 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 16/10 (2013.01); G11C 2013/0088 (2013.01); G11C 2207/2209 (2013.01);
Abstract

A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.


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