The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Dec. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kermin E. Fleming, Jr., Hudson, MA (US);

Kent D. Glossop, Merrimack, NH (US);

Simon C. Steely, Jr., Hudson, NH (US);

Jinjie Tang, Acton, MA (US);

Alan G. Gara, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0862 (2016.01); G06F 12/0842 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 9/3005 (2013.01); G06F 9/3016 (2013.01); G06F 9/3802 (2013.01); G06F 9/3861 (2013.01); G06F 12/0842 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01); G06F 2212/602 (2013.01); G06F 2212/62 (2013.01);
Abstract

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform a second operation when an incoming operand set arrives at the plurality of processing elements.


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