The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Jun. 27, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Der Chih, Hsinchu, TW;

Chia-Fu Lee, Hsinchu, TW;

Chien-Yin Liu, Hsinchu, TW;

Yi-Chun Shih, Taipei, TW;

Kuan-Chun Chen, Hsinchu, TW;

Hsueh-Chih Yang, Hsinchu, TW;

Shih-Lien Linus Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/29 (2006.01); H03M 13/15 (2006.01); H03M 13/19 (2006.01); G11C 29/42 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 11/1012 (2013.01); G06F 11/1048 (2013.01); H03M 13/2906 (2013.01); H03M 13/2909 (2013.01); H03M 13/2927 (2013.01); G11C 29/42 (2013.01); H03M 13/152 (2013.01); H03M 13/1515 (2013.01); H03M 13/19 (2013.01);
Abstract

A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.


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