The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Jul. 19, 2017
Applicants:

Tariq Salim Alsaiary, Jeddah, SA;

Ibrahim Abdullah Alhomoudi, Alholaliah Town, SA;

Inventors:

Tariq Salim Alsaiary, Jeddah, SA;

Ibrahim Abdullah Alhomoudi, Alholaliah Town, SA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 31/036 (2006.01); G01L 9/00 (2006.01); B81C 1/00 (2006.01); B81B 7/02 (2006.01); G01L 19/14 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00246 (2013.01); B81B 7/02 (2013.01); B81C 1/00269 (2013.01); G01L 9/0042 (2013.01); G01L 9/0045 (2013.01); G01L 9/0054 (2013.01); G01L 9/0072 (2013.01); G01L 19/147 (2013.01);
Abstract

Monolithic integration of microelectromechanical systems (MEMS) sensors with complementary oxide semiconductor (CMOS) electronics for pressure sensors is a very challenging task. This is primarily due to the requirement for a very high quality thin diaphragm to provide the pressure dependent MEMS deformation that can be sensed and, when seeking absolute rather than relative pressure sensors, a sealed reference cavity. Accordingly, a new manufacturing process is established based upon back-etching and bonding of a monolithic absolute silicon carbide (SiC) capacitive pressure sensor. Beneficially, the process embeds the critical features of the MEMS within a shallow trench formed within the silicon substrate and then processing the CMOS circuit. The process further benefits as it maintains that those elements of the MEMS element fabrication process that are CMOS compatible are implemented concurrently with those CMOS steps as well as the metallization steps. However, the CMOS incompatible processing is partitioned discretely.


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