The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
May. 05, 2016
Applicant:
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Inventor:
Yonggen He, Shanghai, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/3115 (2006.01); H01L 21/324 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0262 (2013.01); H01L 21/0273 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/31155 (2013.01); H01L 21/324 (2013.01); H01L 21/823418 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/45 (2013.01); H01L 29/6656 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 21/0228 (2013.01); H01L 21/02271 (2013.01); H01L 21/02274 (2013.01);
Abstract
A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.