The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

May. 21, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ming Zhu, Singapore, SG;

Hui-Wen Lin, Taiping, TW;

Harry Hak-Lay Chuang, Singapore, SG;

Bao-Ru Young, Zhubei, TW;

Yuan-Sheng Huang, Taichung, TW;

Ryan Chia-jen Chen, Chiayi, TW;

Chao-Cheng Chen, Shin-Chu, TW;

Kuo-Cheng Ching, Zhubei, TW;

Ting-Hua Hsieh, Hsinchu, TW;

Carlos H. Diaz, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28088 (2013.01); H01L 21/82345 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01);
Abstract

A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.


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