The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Dec. 07, 2018
Applicants:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Sumitomo Electric Device Innovations, Inc., Kanagawa, JP;

Inventors:

Chihoko Mizue, Yokohama, JP;

Tomohiro Yoshida, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 29/41725 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/78 (2013.01); H01L 29/2003 (2013.01);
Abstract

A transistor type of field effect transistor (FET) having a field plate is disclosed. The FET provides an active region and two inactive regions sandwiching the active region therebetween, where the electrodes are provided in the active region. The FET further includes fingers and buses of the drain and the source. The fingers overlap with the electrodes of the drain and the source; while the busses are provided in respective inactive regions. The field plate includes a field plate finger and a field plate interconnection. The field plate finger extends parallel to the gate electrode in a side facing the drain electrode. The field plate interconnection connects the field plate finger with the source interconnection in the inactive region opposite to the inactive region where the drain bus exists.


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