The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Jul. 20, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Tsutomu Tezuka, Yokohama, JP;

Fumitaka Arai, Yokkaichi, JP;

Keiji Ikeda, Kawasaki, JP;

Tomomasa Ueda, Yokohama, JP;

Nobuyoshi Saito, Tokyo, JP;

Chika Tanaka, Fujisawa, JP;

Kentaro Miura, Kawasaki, JP;

Tomoaki Sawabe, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); G11C 16/04 (2006.01); H01L 29/66 (2006.01); G11C 5/06 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 27/11582 (2017.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); G11C 5/06 (2013.01); G11C 11/5671 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01);
Abstract

According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.


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