The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Jun. 06, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Matthew G. Dayley, Plymouth, CA (US);

Yadhu Vamshi S. Vancha, Rancho Cordova, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G05F 3/08 (2006.01); G11C 7/14 (2006.01); G11C 27/02 (2006.01); G05F 3/26 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G05F 3/08 (2013.01); G05F 3/26 (2013.01); G11C 7/10 (2013.01); G11C 7/14 (2013.01); G11C 27/02 (2013.01); G11C 27/024 (2013.01);
Abstract

A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.


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