The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 04, 2020

Filed:

Dec. 26, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Carlos V. Rozas, Portland, OR (US);

Ittai Anati, Ramat Hasharon, IL;

Francis X. McKeen, Portland, OR (US);

Krystof Zmudzinski, Forest Grove, OR (US);

Ilya Alexandrovich, Yokneam Illit, IL;

Somnath Chakrabarti, Portland, OR (US);

Dror Caspi, Kiryat Yam, IL;

Meltem Ozsoy, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 3/06 (2006.01); G06F 12/0806 (2016.01); G06F 12/0868 (2016.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01); G06F 12/128 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 3/065 (2013.01); G06F 3/068 (2013.01); G06F 3/0619 (2013.01); G06F 12/0806 (2013.01); G06F 12/0868 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 12/128 (2013.01); G06F 12/145 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/621 (2013.01); G06F 2212/657 (2013.01); G06F 2212/68 (2013.01);
Abstract

A secure enclave circuit stores an enclave page cache map to track contents of a secure enclave in system memory that stores secure data containing a page having a virtual address. An execution unit is to, in response to a request to evict the page from the secure enclave: block creation of translations of the virtual address; record one or more hardware threads currently accessing the secure data in the secure enclave; send an inter-processor interrupt to one or more cores associated with the one or more hardware threads, to cause the one or more hardware threads to exit the secure enclave and to flush translation lookaside buffers of the one or more cores; and in response to detection of a page fault associated with the virtual address for the page in the secure enclave, unblock the creation of translations of the virtual address.


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