The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
Jun. 01, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Grzegorz Jereczek, Gdansk, PL;
Pawel Lebioda, Robakowo, PL;
Maciej Maciejewski, Gdansk, PL;
Pawel Makowski, Gdansk, PL;
Piotr Pelplinski, Sopot, PL;
Jakub Radtke, Gdansk, PL;
Aleksandra Wisz, Gdansk, PL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/06 (2006.01); G06F 9/30 (2018.01); G06F 12/0862 (2016.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0607 (2013.01); G06F 9/30036 (2013.01); G06F 12/0862 (2013.01); G11C 7/1042 (2013.01);
Abstract
An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
Quick Actions:
Jereczek, Grzegorz. (2020). Interleave set aware object allocation (U.S. Patent No. 10552319). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10552319
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile