The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2020
Filed:
Mar. 13, 2018
Applicant:
Fujitsu Semiconductor Limited, Yokohama-shi, Kanagawa, JP;
Inventors:
Yasunori Uchino, Kuwana, JP;
Kenichi Watanabe, Kuwana, JP;
Assignee:
FUJITSU SEMICONDUCTOR LIMITED, Kanagawa, JP;
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); G06F 17/5068 (2013.01); G06F 17/5077 (2013.01); H01L 21/76802 (2013.01); H01L 21/76807 (2013.01); H01L 21/76808 (2013.01); H01L 21/76877 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.