The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

May. 10, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Amit Verma, Uttar Pradesh, IN;

Suyash Kumar, Uttar Pradesh, IN;

Habeeb Farah, Nazareth, IL;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/504 (2013.01); G06F 17/5022 (2013.01); G06F 17/5036 (2013.01); G06F 17/505 (2013.01); G06F 17/5045 (2013.01); G06F 17/5081 (2013.01); H01L 27/0207 (2013.01);
Abstract

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.


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