The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Jan. 22, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Aaron Willey, Hayward, CA (US);

Hari Anand Ravi, Bangalore, IN;

H. Md. Shuaeb Fazeel, Bangalore, IN;

Thomas Evan Wilson, Laurel, MD (US);

Moo Sung Chae, Cary, NC (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/287 (2013.01); G06F 2213/28 (2013.01);
Abstract

Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.


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