The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David M. Durham, Beaverton, OR (US);

Kai Cong, Hillsboro, OR (US);

Vedvyas Shanbhogue, Austin, TX (US);

Barry E. Huntley, Hillsboro, OR (US);

Jason W. Brandt, Austin, TX (US);

Siddhartha Chhabra, Portland, OR (US);

Ravi L. Sahita, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 12/14 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/65 (2013.01);
Abstract

An embodiment of a semiconductor package apparatus may include technology to identify a first encrypted memory alias corresponding to a first portion of memory based on a verification indicator, where the first portion is decryptable and readable by both a privileged component and an unprivileged component, and identify a second encrypted memory alias corresponding to a second portion of memory based on the verification indicator, where the second portion is accessible by only the unprivileged component. Other embodiments are disclosed and claimed.


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