The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 28, 2020

Filed:

Oct. 23, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Neven M Abou Gazala, Kirkland, WA (US);

Paul S. Diefenbaugh, Portland, OR (US);

Nithyananda S. Jeganathan, Portland, OR (US);

Eugene Gorbatov, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 12/0868 (2016.01); G06F 12/0804 (2016.01);
U.S. Cl.
CPC ...
G06F 9/46 (2013.01); G06F 12/0868 (2013.01); G06F 12/0804 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/286 (2013.01); Y02D 10/13 (2018.01);
Abstract

Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.


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