The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

Sep. 04, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Po-Lin Chen, Tainan, TW;

Tsung-Hsun Wu, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/11 (2006.01); G11C 11/413 (2006.01); H01L 27/02 (2006.01); G11C 11/412 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01); H01L 27/0207 (2013.01); H01L 27/1211 (2013.01);
Abstract

The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least two inverters coupled to each other for storing data, each inverter comprising an L-shaped gate structure on a substrate, the L-shaped gate structure includes a first portion arranged along a first direction and a second portion aligned along a second direction, wherein the first portion crosses a first diffusion region to form a pull-up device, and the first portion crosses a second diffusion region and a third diffusion region to form a pull-down device, and each of the inverters includes a local interconnection layer, crossing the second diffusion region and the third diffusion region.


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