The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
Nov. 13, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventor:
John Guzek, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 21/683 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 25/16 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/6835 (2013.01); H01L 23/3114 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/82 (2013.01); H01L 25/105 (2013.01); H01L 25/16 (2013.01); H01L 21/568 (2013.01); H01L 24/20 (2013.01); H01L 2221/68359 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/19 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/2105 (2013.01); H01L 2224/221 (2013.01); H01L 2224/821 (2013.01); H01L 2224/8234 (2013.01); H01L 2224/8236 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01057 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01);
Abstract
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.