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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10541186 B1

PDFFull Text
Date of Patent:
Jan. 21, 2020

Filed:

Apr. 11, 2018

Chip package and chip packaging method

Applicant:

China Wafer Level Csp Co., Ltd., Suzhou, Jiangsu, CN;

Inventors:

Zhiqi Wang, Suzhou, CN;

Guoliang Xie, Suzhou, CN;

Hanqing Hu, Suzhou, CN;

Assignee:

China Wafer Level CSP Co., Ltd., Suzhou, Jiangsu, CN;

Attorney:

Wolf, Greenfield & Sacks, P.C.

Primary Examiner:

Elias Ullah

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 27/146 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/78 (2013.01); H01L 24/06 (2013.01); H01L 24/96 (2013.01); H01L 27/14618 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14687 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68386 (2013.01); H01L 2224/11002 (2013.01); H01L 2224/113 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/95001 (2013.01);
Abstract

A chip package and a chip packaging method are provided. The package includes: a chip to be packaged, a reinforcing layer and solder bumps. The chip to be packaged includes a first surface and a second surface opposite to each other, the first surface includes a sensing region and first contact pads, and the first contact pads are electrically coupled to the sensing region. The reinforcing layer covers the first surface of the chip to be packaged. The solder bumps are provided on the second surface of the chip to be packaged. The solder bump is electrically connected to the first contact pad and is configured to electrically connect with an external circuit.

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