The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
Apr. 03, 2018
Cadence Design Systems, Inc., San Jose, CA (US);
Craig Franklin Deaton, Rowlett, TX (US);
Abner Luis Panho Marciano, Belo Horizonte-Minas Gerais, BZ;
Matheus Nogueira Fonseca, Betim-Minas Gerais, BZ;
Ronalu Augusta Nunes Barcelos, Belo Horizonte-Minas Gerais, BZ;
Fabiano Cruz Peixoto, Belo Horizonte, BZ;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.