The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 21, 2020

Filed:

May. 10, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Krystof C. Zmudzinski, Forest Grove, OR (US);

Carlos V. Rozas, Portland, OR (US);

Francis X. McKeen, Portland, OR (US);

Rebekah M. Leslie-Hurd, Portland, OR (US);

Meltem Ozsoy, Hillsboro, OR (US);

Somnath Chakrabarti, Portland, OR (US);

Mona Vij, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/1027 (2016.01); G06F 12/1009 (2016.01); G06F 12/14 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 12/1408 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01);
Abstract

Translation lookaside buffer (TLB) tracking and managing technologies are described. A processing device comprises a translation lookaside buffer (TLB) and a processing core to execute a virtual machine monitor (VMM), the VMM to manage a virtual machine (VM) including virtual processors. The processing core to execute, via the VM, a plurality of conversion instructions on at least one of the virtual processors to convert a plurality of non-secure pages to a plurality of secure pages. The processing core also to execute, via the VM, one or more allocation instructions on the at least one of the virtual processors to allocate at least one secure page of the plurality of secure pages, execution of the one or more allocation instructions to include determining whether the TLB is cleared of mappings to the at least one secure page prior to allocating the at least one secure page.


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