The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Mar. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alpa T. Narendra Trivedi, Hillsboro, OR (US);

Siddhartha Chhabra, Hillsboro, OR (US);

David M. Durham, Beaverton, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 9/32 (2006.01); G06F 9/455 (2018.01); G06F 21/57 (2013.01);
U.S. Cl.
CPC ...
H04L 9/3234 (2013.01); G06F 9/45558 (2013.01); G06F 21/575 (2013.01); H04L 63/061 (2013.01); G06F 2009/45583 (2013.01);
Abstract

This disclosure is directed to cryptographic protection for trusted operating systems. In general, a device may comprise for example, at least processing circuitry and memory circuitry. The device may be virtualized in that the processing circuitry may load virtual machines (VMs) and a virtual machine manager (VMM) into the memory circuitry during operation. At least one of the VMs may operate as a trusted execution environment (TEE) including a trusted operating system (TOS). The processing circuitry may comprise encryption circuitry to cryptographically protect the TOS. For example, the VMM may determine a first memory range in which the TOS will be loaded and store data regarding the first memory range in a register within the encryption circuitry. The register configures the encryption circuitry to cryptographically protect the TOS.


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