The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 14, 2020
Filed:
May. 16, 2019
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/94 (2006.01); H01L 27/11575 (2017.01); H01L 49/02 (2006.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11575 (2013.01); H01L 27/1157 (2013.01); H01L 27/11573 (2013.01); H01L 28/87 (2013.01); H01L 28/88 (2013.01); H01L 28/91 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/42352 (2013.01); H01L 29/66181 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/945 (2013.01);
Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.