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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10535674 B1

PDFFull Text
Date of Patent:
Jan. 14, 2020

Filed:

Jul. 19, 2017

Method of forming a semiconductor device structure and semiconductor device structure

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Juergen Faul, Radebeul, DE;

Frank Jakubowski, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:

Amerson Law Firm, PLLC

Primary Examiner:

Charles D Garber

Assistant Examiner:

Steven M Christopher

Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 21/762 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3065 (2006.01); H01L 21/265 (2006.01); H01L 27/11521 (2017.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 27/11582 (2017.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76283 (2013.01); H01L 27/11521 (2013.01); H01L 27/11582 (2013.01); H01L 27/1207 (2013.01); H01L 28/00 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42336 (2013.01); H01L 29/42352 (2013.01);
Abstract

A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

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