The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Feb. 07, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Daniel B. Penney, Wylie, TX (US);

Liang Chen, Allen, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/18 (2006.01); G11C 7/10 (2006.01); G06F 5/06 (2006.01); G06F 13/42 (2006.01); G11C 29/50 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G06F 5/06 (2013.01); G06F 13/1689 (2013.01); G06F 13/4234 (2013.01); G11C 7/1036 (2013.01); G11C 7/1051 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 29/50012 (2013.01); G11C 2207/107 (2013.01);
Abstract

Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.


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