The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 2020

Filed:

Dec. 24, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Carlos V. Rozas, Portland, OR (US);

Ilya Alexandrovich, Haifa, IL;

Gilbert Neiger, Hillsboro, OR (US);

Francis X. McKeen, Portland, OR (US);

Ittai Anati, Haifa, IL;

Vedvyas Shanbhogue, Austin, TX (US);

Mona Vij, Hillsboro, OR (US);

Rebekah Leslie-Hurd, Portland, OR (US);

Krystof C. Zmudzinski, Forest Grove, OR (US);

Somnath Chakrabarti, Bangalore, IN;

Vincent R. Scarlata, Beaverton, OR (US);

Simon P. Johnson, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); H04L 9/32 (2006.01); G06F 12/0802 (2016.01); H04L 9/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 12/0802 (2013.01); G06F 12/1466 (2013.01); H04L 9/14 (2013.01); H04L 9/32 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01); G06F 2212/60 (2013.01);
Abstract

Instructions and logic support suspending and resuming migration of enclaves in a secure enclave page cache (EPC). An EPC stores a secure domain control structure (SDCS) in storage accessible by an enclave for a management process, and by a domain of enclaves. A second processor checks if a corresponding version array (VA) page is bound to the SDCS, and if so: increments a version counter in the SDCS for the page, performs an authenticated encryption of the page from the EPC using the version counter in the SDCS, and writes the encrypted page to external memory. A second processor checks if a corresponding VA page is bound to a second SDCS of the second processor, and if so: performs an authenticated decryption of the page using a version counter in the second SDCS, and loads the decrypted page to the EPC in the second processor if authentication passes.


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