The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2020
Filed:
Dec. 28, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Chooi Pei Lim, Bayan Baru, MY;
Teik Wah Lim, Bayan Lepas, MY;
Boon Haw Ooi, Bayan Lepas, MY;
Keong Hong Oh, Bayan Lepas, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G06F 17/5054 (2013.01); H03K 19/17704 (2013.01); H03K 19/17708 (2013.01); H03K 19/17724 (2013.01); H03K 19/17736 (2013.01); H03K 19/17744 (2013.01);
Abstract
The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.